This invention relates generally to electrostatic discharge (ESD) protection circuits for silicon-on-insulator (SOI) circuits. More particularly, it relates to a novel protection circuit structure for providing improved electrostatic discharge protection capability to silicon-on-insulator circuits.
As is generally well-known in the art, silicon-on-insulator (SOI) technology has become considered as one of the most effective techniques for fabricating high-speed MOS and CMOS circuits in very large scale integrated (VLSI) circuits. In accordance with the SOI technique, a thin epitaxial layer of semiconductor material, such as silicon, is deposited on an insulator (e.g., a buried oxide film) so as to reduce the capacitive coupling between the semiconductor layer and the underlying insulator and substrate material and thus preventing latch-up. Therefore, field-effect transistors and other devices formed within the thin epitaxial layer of semiconductor material have an advantage of high-speed switching characteristics than the integrated circuits of the same dimension fabricated on a traditional bulk silicon substrate.
However, these SOI circuits, like other MOS-type circuits, are particularly susceptible to being damaged or even destroyed by electrostatic discharge. In particular, the magnitude of an electric voltage allowed to be applied to the thin gate insulators of the MOS and CMOS transistors is rather limited since their physical size thereof is fairly small. Thus, such static discharge by persons or equipment handling the integrated circuits can be of a catastrophic nature with sufficient energy so as to cause permanent damage of the semiconductor elements therein.
In order to protect the semiconductor elements formed in the bulk silicon substrate from electrostatic discharge, ancillary protection circuits were provided and the energy would be dissipated through the bulk silicon substrate on which the circuits were fabricated. On the other hand, the ancillary protection circuits, such as diode circuits, in the bulk substrate do not perform well in the SOI circuits. This is due to the fact that the insulating layer (buried film oxide) in the SOI circuits is a poor thermal conductor and thus all of the energy must be dissipated laterally through the diodes formed in the thin semiconductor layer. As a result, this leads to increased heat being generated during the ESD event since the buried oxide film has inferior thermal conducting characteristics as compared to the bulk silicon.
Accordingly, there still exists a need for a protection circuit structure for use with silicon-on-insulator circuits so as to provide enhanced electrostatic discharge protection. Further, it would be desirable for the protection circuit structure to readily serve as a heat sink so as to dissipate the thermal energy created in the thin semiconductor layer of the SOI structure.
Accordingly, it is a general object of the present invention to provide a novel protection circuit structure for use with silicon-on-insulator circuits which has traditionally been unavailable heretofore.
It is an object of the present invention to provide a protection circuit structure for providing improved electrostatic discharge protection capability to silicon-on-insulator circuits.
It is another object of the present invention to provide a protection circuit structure for use with silicon-on-insulator circuits which can serve as a heat sink so as to dissipate the thermal energy during an ESD event.
It is still another object of the present invention to provide a protection circuit structure for use with silicon-on-insulator circuits which includes a protection diode formed underneath an electrically conductive input or input/output pad.
In a preferred embodiment of the present invention, there is provided a protection circuit structure for providing electrostatic discharge protection capability to silicon-on-insulator integrated circuits. A SOI structure includes a transistor device having a source region, a drain region, and a channel region all formed over an insulating layer. The insulating layer is formed over a p-type silicon substrate. A thin oxide layer is formed over the insulating layer. A p-type conductive region is formed in an upper portion of the insulating layer. A metal conductive region is formed in the center of the p-type conductive region and extends between top and bottom surfaces thereof. An n-type conductive region is formed in the p-type silicon substrate adjacent to the bottom surface of the p-type conductive region so as to define a protection diode with the p-type silicon substrate. An electrically conductive input or input/output pad is formed over the top surface of the n-type conductive region. A conductive lead line is operatively joined between the input or input/output pad and one of the source and drain regions of the transistor device.